Jensen Huang anticipates 20% performance boost from gate-all-around transistors

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During a Q&A session at the GPU Technology Conference, Huang estimated a roughly 20% performance uplift from transitioning to GAA architecture.


His comments offer an early indication of the company's expectations for future graphics chip designs


TSMC and Intel have touted GAA transistors as a key technology for process nodes beyond 3nm. Recent nodes, including 3nm, have employed FinFET, a structure where the transistor gate surrounds the current channel on three sides.


However, as bleeding-edge transistors shrink and become more densely packed in advanced nodes, electrical leakage becomes a growing concern.



GAA addresses this issue by stacking current channels vertically, increasing the total channel area while allowing gates to surround the channels on all four sides.


Although the technique is more expensive, it enhances both performance and energy efficiency.

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Intel's upcoming 18A node will introduce GAA with Panther Lake laptop CPUs and Clearwater Forest server processors later this year.


TSMC plans to adopt GAA for its 2nm N2 process, which is nearing production and is expected to debut in the iPhone 18 Pro's A20 SoC in late 2026.


At GTC, Huang officially revealed Nvidia's next GPU generation, Vera Rubin, which will be built on TSMC's N3 node and is expected to become available to enterprise clients next year.



Source - Techspot 


Signing off

@Rahul S


@iQOO Connect


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